EMPLOYABILITY OF DIGITAL IMAGE PROCESSING APPLICATION IN FPGA AND ASIC IMPLEMENTATION OF SYSTOLIC ARRAYS FOR THE DESIGN OF OPTIMIZED MEDIAN FILTER

Anoushka Gupta

Vol. 4, Jan-Dec 2018

Page Number: 232-238

Abstract:

Background/Objectives: A new systolic algorithm for median filtering is analyzed in this paper; this algorithm is suitable for VLSI implementation to design an optimized median filter. Methods/Statistical analysis: The modified sort algorithm avoiding the main problem of the median filter is its high computational cost (for sorting N pixels, the temporal complexity is O (N·log N), even with the most efficient sorting algorithms, the clock cycle time is equal to the propagation delay of a simple comparator circuit. Results/Findings: The hardware requirements of the architecture are significantly lower than those of previously reported systolic array architectures. An implementation of an 8-bit word length 3X3 window size filter in an ALTERA EP1C3T100C6 FPGA achieved a clock rate in excess of 197 MHz with 85 cells only.Conclusion/Application: An improved algorithm has been proposed to address the problem of a median filter that is high computation time is encountered.

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